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149. Apple A2159 timing analysis- Distribution of clock signals
We will learn about the distribution of clock signals in the Apple A2159 circuit.

Hello everyone, today we will learn about the distribution of clock signals in the Apple A2159 circuit

When we talked about power supply, PG, clock, and reset circuit in the last video,

we introduced its step 44, the CPU outputs various clocks,

so what are the various clocks here?

Let's take a look

This whole block diagram is about the clock signal

After each power supply is normal,

the 24MHz crystal oscillator of the CPU starts to vibrate,

and the external name is PCH_CLK24M_XTALIN

This pin is connected to the pin of the crystal

The location number of the crystal oscillator is Y1900

After the crystal oscillator starts to vibrate, it provides the CPU with a reference clock frequency

Then, this clock module will output various clocks

Let's find out

First, CLKOUT_PCIE_N0 and CLKOUT_PCIE_P0, this is a pair of PCIE bus clocks

It has group 0, group 1, group 2, until group 5,

a total of 6 groups of PCIE bus clocks

Each group has a clock request signal, which is active at low level

When the request signal is low, the CPU will output a corresponding set of clocks

If the request signal is always high, the CPU will not output the clock

External names starting with NC are floating and not used

This is the clock used for DEBUG diagnosis

The following group is sent to the SOC, that is, to the T2 chip,

and the T2 chip pulls down the clock request signal

CPU will output this set of 100MHz PCIE bus clock to the T2 chip

PCIE bus clocks are differential clocks

The following group is for the TBT Thunderbolt chip

Next, the group starting with NC is not used

The fourth group below, this is the PCIE bus clock for the wireless network card

After the wireless network card lowers the request signal,

the CPU will output a corresponding set of PCIE bus clocks to the wireless network card

The following one is also floating and not used

Then, here is a set of test clocks, which are also not used

OK, next, here are a few signals

First of all, this is the reset signal of the RTC circuit,

it does not belong to the clock circuit, it belongs to the RTC circuit

RTCX1/ RTCX2, these two pins were originally connected to the 32.768KHz crystal oscillator of the RTC circuit

But here they are not connected to the crystal oscillator,

but the 32.768KHz clock is provided externally to the RTC circuit

This is from the PMU power chip

This pin is grounded through a resistor, and this CLKIN_XTAL is the input clock

This is also grounded through a resistor and is not used

These two pins are grounded through a resistor, which are also not used

This is the pin connected to the 24MHz crystal oscillator, which we just introduced

SUSCLK is the 32.768KHz clock output by the PCH,

which is generally not used by external circuits, it is floating

Ok, this is the distribution of the clock signal

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